This invention relates to the planarization of integrated circuit surfaces, particularly the planarization of the layers of dielectric or electrically insulative material which are used for passivation and electrical insulation at various levels of integrated circuits.
In the construction of high density integrated circuits utilizing conventional thin film techniques and structures wherein electrically insulative layers such as silicon dioxide or silicon nitride are deposited by conventional chemical vapor or sputter deposition techniques over underlying metallization patterns, the insulative layer tends to follow the contours of the underlying metallization lines. In other words, a line in the metallization pattern will result in a corresponding elevation in the covering insulative layer over the metallization pattern. In integrated circuits having multi-levels of metallization, the cumulative effect of such elevation in the insulative layers is highly undesirable.
For example, a line in the metallization pattern may result in a corresponding elevation in the covering dielectric layer over the metallization pattern. Then, after a subsequent level metallization pattern is deposited onto the covering layer and it, in turn, covered by an additional insulative layer, the upper surface of the additional covering layer will display the cumulative effects of both underlying metallization patterns. We have, in such cases, a "skyscraper" effect wherein the cumulative metallic lines produce pronounced elevations which render the surface of an uppermost insulative layer so irregular that metallization lines deposited over such a layer extend over a very bumpy surface. This tends to produce discontinuities in the metal lines.
In addition, in such structures, it is difficult to design a structure in which a via hole through a given covering layer of dielectric material to an underlying metallization line may be made with consistent control so as to avoid over-etching through the insulative layer under the metallization, thereby shorting out the conductive line through its underlying insulation.
The problems with such elevation and irregularity in integrated circuit levels are discussed in detail in U.S. Pat. No. 3,804,738.
In addition, undesirable elevations in integrated circuit surfaces, particularly in the surfaces of insulative layers, present a problem in the formation of dielectrically isolated integrated circuits. Such dielectrically isolated integrated circuits are characterized by patterns of moats or trenches extending from the surface of a semiconductor substrate to isolate respectively a plurality of pockets on the semiconductor material. Where the dielectric or insulative layers are deposited over such mesa-like structures, the result is a pattern of steps or elevations in the insulated layer corresponding to the pattern of mesas in the substrate. Depending on the techniques utilized to fill the trenches or moats with dielectric material, these steps may often be quite steep which, as previously mentioned, could result in discontinuities in the metallization placed on the insulative layer.
In order to avoid such variation in the insulative layer, one approach in the art has been to oxidize the silicon substrate surrounding the trench or moat by heating to form thermal oxide which fills in the trench providing the lateral insulation and a relatively planar surface upon which surface insulative layers can thereafter be applied. This process is described in detail in an article entitled "Local Oxidation of Silicon and Its Applications in Semiconductor Device Technology", J. A. Appels, et al., Phillips Research Reports 25, page 118, (1970).
While this approach may be used in methods where it is possible to oxidize the substrate in situ to fill in the trenches, the art has yet to develop a practical approach wherein planarization may be achieved in a method wherein the trenches are filled with the dielectric or insulative material by deposition techniques such as vapor deposition or RF sputter deposition. The problems involved in the planarization of such deposited insulative layers are essentially the same as those previously described with respect to planarization of insulative layers over a metallization pattern except that the steps or elevations often tend to be even higher, thereby making the problem even more difficult.
In the prior art, primarily two approaches have been offered for lowering the elevations or steps in such insulative layers to, thereby, planarize the surface. The first approach involves resputtering of the elevations. Although this approach has been effective in planarizing elevations of relatively narrow widths, it is relatively time-consuming. In fact, the time factor becomes so pronounced that the resputtering approach becomes relatively burdensome where the elevations or steps are relatively wide.
The second approach involves masking the depressed areas or valleys with an etch-resistant material such as photoresist through conventional photolithographic techniques, and then etching to remove the uncovered elevations or steps. This approach often runs into problems with photoresist mask alignment. In high density large scale integrated circuits, the dimensions are so minute that difficulties may be encountered in obtaining the exact registration required to completely mask the depressed areas or valleys with photoresist. Any misalignment which leaves a portion of a depressed area exposed could result in an etch through the insulative layer in said depressed area simultaneously with the planarization of the elevated area. This will result in an undesirable short circuit path through the insulative layer in the depressed area.